XJTAG v2.0 boundary scan system sets new standard for PCB debug & test Monday 29 October 2007 PDF Print - XJTAG to unveil version 2.0 at Productronica (Area A1/Booth 448), November 13-16 2007, New Munich Trade Fair Center, Germany - XJTAG v2.0 automates JTAG chain set-up and enables quick and easy categorisation of non-JTAG/cluster devices - New built-in netlist explorer provides a simple interface to view connectivity between devices - Other enhancements include improved memory test, real-time DFT test coverage analysis, an extended library of device-centric test scripts, improved integration with LabVIEW, and support for Xilinx’s Virtex-5 FPGA System Monitor CAMBRIDGE, England, October 29, 2007 – XJTAG, a leading supplier of IEEE Std. 1149.1 compliant boundary scan development tools, today announced version 2.0 of its popular XJTAG boundary scan development system, which sets a new standard for speed and accuracy of printed circuit board (PCB) debug and test. The new version of the XJTAG system - which is used throughout the electronic product life cycle by board developers and manufacturers to debug, test and program complex Ball Grid Array (BGA) populated printed circuit boards and systems - will be unveiled by XJTAG at Productronica (Area A1/Booth 448), New Munich Trade Fair Center, Germany, November 13-16, 2007. XJTAG 2.0 has a raft of new features, including automated JTAG chain discovery and set-up, a built-in netlist explorer, optimised memory test, and real-time design for test (DFT) coverage tracking. It also includes an ever growing library of device-centric test scripts, improved integration with LabVIEW, and support for Xilinx’s Virtex-5 FPGA System Monitor. Simon Payne, CEO at XJTAG, said: “Engineers invariably choose the XJTAG boundary scan system because it’s so easy-to-use and because you get everything for debugging and testing complex PCBs in one package for a set price and with no hidden extras. “While developing the new version, we have listened closely to feedback from our fast-growing base of customers - both design engineers and manufacturers - and have focused on further abstracting engineers from the complexity of the JTAG/ IEEE1149.1 standard, in particular, through enhancements to our XJEase programming environment.” With version 2.0, XJTAG has introduced a drag-and-drop interface that automates the JTAG chain discovery and set-up process, thereby saving engineers time and hassle. The developer simply connects the computer to the unit under test via the USB2.0 XJLink hardware module, creates a new project, and adds the target board. The XJTAG system then detects the scan chain and matches the JTAG device codes to their respective BSDL files, as well as identifying ground nets and making intelligent suggestions about other components. In addition, this intelligent set-up facility enables the board developer to quickly and easily categorise all of the non-JTAG or cluster devices in the circuit. For example, with one click all the pull resistors, or another component type, can be grouped together for speed and convenience during the set-up stage. XJTAG version 2.0 also includes a built-in netlist explorer that provides a simple interface to view the connectivity between devices on the board. Other enhancements include an optimised memory test, real-time Design For Test (DFT) coverage analysis, an extended library of device-centric test scripts, and improved integration with LabVIEW and other leading test executives. XJTAG has also added support for Xilinx’s Virtex-5 FPGA System Monitor to enable customers to check power supplies or perform overall thermal management using the JTAG port on the 65-nm Virtex-5 FPGAs. Dominic Plunkett, chief technology officer at XJTAG, said: “In today’s right-first-time environment, engineers need a test solution that not only maximises test coverage but also minimises board debug time. Using XJTAG, engineers are able to create valuable test IP, which can be recorded, refined and repeatedly re-used throughout the development cycle. With XJTAG v2.0, customers will continue to have an ‘all-in-one’ boundary scan system that enables them to get their boards up and running in minutes and hours not days and weeks as is the case with some traditional systems.” The XJTAG development system is a cost-effective ‘out-of-the-box’ solution for debugging, testing and programming electronic printed circuits boards and systems throughout the product lifecycle. The XJTAG system reduces the time and cost of board development and prototyping by allowing early test development, early design validation of CAD netlists, fast generation of highly functional tests and test re-use across circuits using the same devices. XJTAG enables engineers to test a high proportion of the circuit (both boundary scan and cluster devices) including BGA and chip scale packages, such as SDRAMs, Ethernet controllers, video interfaces, Flash memories, FPGAs and microprocessors. XJTAG also enables In-System Programming of FPGAs, CPLDs and Flash memories. The XJTAG system incorporates a number of easy to use software tools. XJEase is a high-level programming language that provides all the functionality to create a complete JTAG test solution. XJAnalyser is a powerful tool for circuit visualisation that provides a simple graphical view of the state of all JTAG pins. XJRunner is a production optimised version of the XJTAG Development System, designed specifically for contract manufacturers and production sites. The development system also contains the XJLink, which is a USB 2.0 interface used to connect the computer to the unit under test. The XJLink contains the XJTAG licences. This enables the system to be used on multiple computers on and off site. XJDemo is a fully populated demonstrator board, with tutorials designed to provide the developer with a rapid understanding of the XJTAG system. The XJTAG Professional Development System adds the XJIO board, which improves the test coverage for a Unit Under Test (UUT) by verifying the signals right through to the external connections. Pricing for the XJTAG system ranges from £3,500 (€5,075) to £9,900 (€14,355). For more information about the XJTAG system, please telephone +44 (0) 1954 213888, facsimile +44 (0) 1954 211565 or email email@example.com. Alternatively visit www.xjtag.com. XJTAG has a global network of distributors servicing Europe, the Far East, North America, the Middle East and Australasia. Photography to accompany this news release is available at: http://www.xjtag.com/company/press/ -ends- About XJTAG (www.xjtag.com) XJTAG is a leading supplier of IEEE Std. 1149.1 compliant boundary scan development tools. Its JTAG (Joint Test Action Group) development system offers a highly competitive solution for designers and developers of electronic printed circuit boards and systems. Utilising XJTAG allows the circuit development and manufacturing process to be shortened significantly by facilitating early test development, early design validation, fast development of functional tests and test re-use across circuits that use the same devices. XJTAG is based in Cambridge, UK, and is part of the Cambridge Technology Group. What is JTAG? Advances in silicon design, such as increasing device density and, more recently, ball grid array (BGA) and chip scale packaging, have made traditional electronic circuit testing methods hard to use. In order to overcome these problems and others; some of the world’s leading silicon manufacturers combined to form the Joint Test Action Group (JTAG). The findings of this group were used as the basis for the Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1: Standard Test Access Port and Boundary Scan Architecture. Media contact (for XJTAG): Martin Brooke Martin Brooke Associates Tel: +44 (0) 1223 244500 Email: firstname.lastname@example.org This press release was distributed by ResponseSource Press Release Wire on behalf of Martin Brooke Associates in the following categories: Computing & Telecoms, for more information visit http://pressreleasewire.responsesource.com/about.