Professor Goldstein, Carnegie Mellon University to Keynote at IEE FPGA Developer's Forum
London, UK - Field-programmable gate array (FPGA) devices based on electronic nanotechnology and in particular molecular electronics hold the key to the future of computing and the sustainability of Moore's Law. This is the view of Professor Seth Goldstein, a keynote speaker at the IEE FPGA Developer's Forum on 21 and 22 October, 2003.
This new class of electronic device, termed chemically assembled electronic nanotechnology (CAEN), will be reconfigurable, low power, defect tolerant and provide very high component densities at significantly reduced manufacturing costs, according to Prof Goldstein, Carnegie Mellon University, US.
"Within 10 years CAEN has the potential to offer orders of magnitude improvements in computing power and complete flexibility in terms of configuration and programming, without the huge upfront non-recoverable engineering costs of developing an ASIC device," said Prof Goldstein.
"Whilst there is still much fundamental research to be completed, CAEN could represent the most significant advancement in the semiconductor industry since the development of CMOS manufacturing techniques in the 1960s," said Goldstein.
Prof Goldstein will present a paper titled "Reconfiguring the Future" on the second day of the IEE FPGA Developer's Forum in London, UK.
Goldstein's work combined with the activities of a number of research institutions in Europe and US shows that CAEN offers the potential to enable electronic circuits to be constructed from single molecule switches interconnected by nanometer sized wires.
CAEN-based devices are constructed from meshes of switches and wires, with a switch at the interconnection of each wire junction. Once programmed a switch holds its state, which means additional devices are not required for programming and that the switch can be programmed and interrogated using the same set of wires. The elegant simplicity of this approach removes much of the overhead required in traditional integrated circuits and means that up to 100 billion switches could be fabricated on a single square centimetre.
Individual switches within a device are very small: a single switch requires 100nm2 as opposed to 100,000nm2 for a traditional CMOS transistor. This provides immediate power saving benefits as nano-scale devices require only a few electrons to cause a switch to change state.
Given the small geometries involved, CAEN is created using chemical self-assembly techniques instead of photolithography.
In one proposed architecture, called a nanoFabric, a hierarchical process is used initially to create the molecular switches followed by two aligned groups of wires to form a two dimensional grid with the switches at the cross points. A separate process is used to create a silicon-based die using standard lithography to provide power, clock lines, and I/O interface and support logic for the grids of switches.
Compared with traditional CMOS, CAEN devices have a higher defect density as a result of their scale and the chemical-based fabrication techniques. Prof Goldstein is leading a team that is developing methods of handling defects through self-diagnosis and then implementing the desired computing functionality by programming around the defects.
Prof Goldstein will report on the latest advances in fabrication, modelling and programming of CAEN devices at the IEE Developer's Forum.
About the IEE
Founded in 1871, the IEE is the largest professional engineering society in Europe and has a worldwide membership of just under 130,000. These men and women, who have joined together to promote the advancement of electrical, electronic and manufacturing science and engineering, range from students to the most distinguished and highly qualified members of the profession.
About The FPGA Developer's Forum
21 and 22 October 2003
FPGA Developers' Forum
The IEE, Savoy Place London
A group of the world's top field-programmable gate array (FPGA) developers have been enlisted to share their expertise with the electronics industry at one of Europe's leading FPGA events, being staged in London by the Institution of Electrical Engineers (IEE).
The IEE FPGA Developers' Forum, supported by Mentor Graphics and Xilinx, will take place on 21 and 22 October, 2003 and will bring together leading industry analysts, technical specialists and commercial developers. The event will be held at The IEE, Savoy Place, London.
This press release was distributed by ResponseSource Press Release Wire on behalf of Speed Communications in the following categories: Consumer Technology, Personal Finance, Business & Finance, Computing & Telecoms, for more information visit https://pressreleasewire.responsesource.com/about.